`timescale 1ns/1ps
`default_nettype none
module imm_gen(
    input  wire [31:0] instr,
    output wire [31:0] imm_i,   // I-type: 31:20
    output wire [31:0] imm_s    // S-type: 31:25|11:7
);
    // I-type: imm[11:0] = instr[31:20]
    assign imm_i = {{20{instr[31]}}, instr[31:20]};

    wire [11:0] imm_s_12 = {instr[31:25], instr[11:7]};
    assign imm_s = {{20{imm_s_12[11]}}, imm_s_12};
endmodule
